Accer8Talent has partnered up with an AI hardware startup who is on a mission to become THE computing platform for LLMs. Founded by highly respected engineering executives who were instrumental in Google’s AI capabilities. They are building processors specifically targeting LLMs as opposed to GPUs, which target all ML models, meaning their performance and efficiency is less optimal for LLMs.
They recently received in $25M in seed funding and expect another round of funding in October.
They are looking for a Principal Level Physical Design Engineer to join their team and help develop top-tier silicon for high-performance and sustainable GenAI. In this role, you will be instrumental in delivering high-performing and functionally accurate silicon for their products, covering compute and memory management.
Job Responsibilities
- You will develop and enhance silicon design and physical design methodologies, creating scalable solutions for blocks, subsystems, and full chip designs from RTL to GDS.
- You will take ownership of entire subsystems or specific subsets and chip-level physical design tasks, including floor-planning, placement, clock insertion, routing, optimization, timing closure analysis, physical verification closure, and electrical analysis.
- You will plan and lead intermediate and final reviews, as well as track execution progress using key PPA metrics, ensuring milestones such as design freeze and tapeout are met.
- You will collaborate closely with design, DFT, and other physical design team members to achieve top-tier performance, power, and area results for the subsystem or block.
Job Requirements
- Minimum 8 years of industry experience in ASIC Physical Design
- Proven track record in floorplanning, place and route, clock tree insertion and analysis, timing analysis, physical verification, electrical sign-off, and related areas, ensuring tapeout-ready GDS for large physical blocks and/or top-level designs.
- Demonstrated ability to collaborate with design, verification, and DFT teams to structure and partition designs optimally for PPA and sign-off.
- Experience working with third-party design services partners, taking subsystems and/or top-level designs from initial floor plan to sign-off and tapeout, is a plus.