Silicon DD Engineer III

Company:  Ursus
Location: Menlo Park
Closing Date: 06/11/2024
Salary: £150 - £200 Per Annum
Hours: Full Time
Type: Permanent
Job Requirements / Description

JOB TITLE: Silicon DD Engineer III

LOCATION: 100% Remote

DURATION: 12 month contract

PAY RANGE: $86-96/hour

TOP 3 SKILLS:

  1. 4+ years of experience as a Digital Design Engineer.
  2. Recent experience with IP RTL coding within the past 2-3 years, specifically for ASIC.
  3. Experience having worked on a design from scratch – code from the ground up.

COMPANY:

Our client is a Fortune 500 multi-national technology company headquartered in Menlo Park, CA.

Role Mandate:

The team is responsible for doing digital design for graphics IP and is looking for an individual to collaborate on uarchitecture development and perform RTL coding on the next version of our IP. This individual will have the opportunity to work on block design implementation for an IP that is going into future AR products.

Role Responsibilities (including, but not limited to):

  1. Own ASIC IP RTL implementation for IP blocks.
  2. Ensure RTL written meets quality checks like Lint/CDC/RDC.
  3. Collaborate closely with design team members, technical leads and the architecture team to ensure the block meets the power and performance requirements.
  4. Collaborate closely with the verification team to develop test plans and review test coverage.
  5. Perform IP integration.
  6. Supervise the RTL-to-GDS flow and assist with synthesis and timing closure.
  7. Work with FPGA engineers to perform early prototyping.
  8. Support hand-off and integration of blocks into larger SOC environments.
  9. Assist with Algorithm analysis.

Must Have Skills:

  1. 4+ years of experience as a Digital Design Engineer.
  2. Recent experience with IP RTL coding within the past 2-3 years, specifically for ASIC.
  3. Experience having worked on a design from scratch – code from the ground up.
  4. Experience in RTL coding and coding for low power in ASICs.
  5. Experience in digital design µArchitecture.
  6. Strong experience with Verilog and SystemVerilog coding.
  7. Perl, Tcl and Python (or similar) scripting experience.

Nice-to-Have Skills:

  1. MSEE/CS or equivalent experience.
  2. Experience developing IP for Graphics Processing Unit (GPU), CPU, Compression, or Video ASICs.
  3. Recent track record of projects where individuals coded from the ground up that were successfully taped out.

Soft Skills:

  1. Strong verbal and written communication skills.

Educational Requirements:

  1. BS Electrical Engineering/Computer Science/Computer Engineering or equivalent experience.

IND123

#J-18808-Ljbffr
Apply Now
Share this job
Ursus
  • Similar Jobs

  • Silicon DD Engineer III

    Menlo Park
    View Job
  • Silicon Validation Engineer

    Sunnyvale
    View Job
  • Silicon Validation Engineer

    Sunnyvale
    View Job
  • Silicon Validation Engineer

    Sunnyvale
    View Job
  • Staff Software Engineer, Silicon

    Sunnyvale
    View Job
An error has occurred. This application may no longer respond until reloaded. Reload 🗙