Principal Verification Engineer

**Job Summary:**
The Principal Verification Engineer will be responsible for architecting and creating verification environments using System-Verilog and Universal Verification Methodology (UVM) IPs and SoCs with embedded CPUs and analog mixed-signal interfaces. They must develop test plans and coverage metrics, create scripts to automate verification processes, perform failure analysis of simulations, and collaborate with design engineers to resolve issues.

**Qualifications:**

• 7+ years of experience in pre-silicon design verification.
• Proficiency in C-shell scripting, Verilog-HDL, and System Verilog.
• Strong knowledge in SV Assertions, UVM/OVM, and functional code coverage.
• Experience with advanced peripheral bus Verification IPs (e.g., GPIO, UART, SPI, SW, JTAG, I2C).
• Proficient with Cadence tools like NC Verilog, NCSIM, and Simvision. Experience with linting tools such as Spyglass is beneficial.
• Independent, self-motivated, with excellent analytical and communication skills.

• Architect and create verification environments using System-Verilog and UVM IPs for IPs and SoCs.
• Develop test plans and coverage metrics, and write block and chip-level tests based on specifications.
• Utilize PERL/Python scripts to automate verification processes and debug.
• Conduct failure analysis of Register Transfer Level and Gate simulations, collaborating with design engineers for resolution.
• Work with architects to define simulation use-case scenarios.