Mask Layout Designer IV

Position: Mask Layout Designer IV
Location: San Diego CA or Sunnyvale CA
Interview: Video
Duration: 6+ months
Description:
As an IC Layout Engineer, you will be a key member of our team, researching, designing and bringing the next-generation of wireless technologies into high-volume production in advanced CMOS technology nodes. Responsibilities include: - Detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, Client/DAC, baseband filters, and bandgap/bias/LDO. - Block level layout through full verification flow including extraction, DRC, LVS, and DFM checking. - Co-work with designers on block level floorplanning. - Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling.
Minimum Qualifications:

• BS and 5+ years of relevant industry experience.
• FinFet experience

Preferred Qualifications:

• Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS.
• Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing.
• Solid understanding of RC delay, electromigration, and coupling.
• Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE, etc.
• High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. in FinFet Technology (7nm experience highly preferred)
• Knowledge of CADENCE layout tools.
• Excellent communication skills and able to work with cross-functional teams.
• Scripting skills in PERL or SKILL are a plus, but not required.

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