Key Responsibilities:
Design and implement RTL for high-performance digital IPs, including but not limited to PCIe, USB, Imaging IPs, high-speed interfaces (SerDes), UCIE, UFS, and DDR.
Collaborate with cross-functional teams to define, design, and verify RTL components.
Participate in the full design cycle, including RTL coding, synthesis, timing analysis, and debugging.
Perform integration of IPs into larger system-on-chip (SoC) designs, ensuring compatibility and performance.
Work closely with verification engineers to develop comprehensive test plans and ensure design functionality.
Debug and resolve design issues related to functionality, timing, or performance.
Optimize RTL code to meet area, power, and performance goals.
Required Qualifications:
Bachelor's or Master's Degree in Electrical Engineering, Computer Engineering, or a related field.
Proven experience in RTL design and implementation.
Hands-on experience with one or more of the following IPs: PCIe, USB, Imaging IPs, SerDes, UCIE, UFS, DDR.
Strong knowledge of Verilog or VHDL for RTL coding.
Experience with high-speed interfaces and protocols.
Proficiency in synthesis tools and timing closure methodologies.
Solid understanding of digital design fundamentals including clocking, resets, low-power design, and DFT.
Experience with RTL verification and debugging using simulation tools.
Desired Skills:
Familiarity with FPGA design and verification tools.
Knowledge of scripting languages (Python, Perl, TCL) for automation purposes.
Strong problem-solving and analytical skills.
Excellent communication and team collaboration abilities.