Sr Design Engineer (AI Chips)

Full-time $180,000.00 - $280,000.00

Posted 11/08/2023

Located in the South San Francisco Bay Area, we are a Semiconductor Startup with over $70M in funding that's on pace to secure our Series C by the end of 2023! We are building a universal processor that combines the functionality of a CPU, GPU, and TPU into one handling some of the largest AI and Machine Learning workloads around.

We are seeking Senior Design Engineers who are local or willing to relocate to the Santa Clara, CA or Las Vegas, NV area that have experience in at least one of the following:

1. High Speed Coherent Interconnect
2. Serial Interfaces
3. PCIe Interface
4. High Speed Cache
5. CPU Execution Unit
6. CPU Fetch Unit
7. Memory Subsystems

Top Reasons to Work with Us

- Competitive salary and benefits package
- Relocation to Santa Clara or Las Vegas
- Opportunities for professional development and advancement
- International environment and further career progression
- Getting in touch with bleeding edge technology
- Flexible working hours, work from home opportunities, and a solid work-life balance
- Collaborative and supportive work environment

What You Will Be Doing

This person will focus on one of the following areas:

1. High Speed Coherent Interconnect
   - Working with a small team to implement, debug, and verify high-speed chip-to-chip interface
   - Building the infrastructure to support bringup and debug in FPGAs and silicon
   - Working with the SW team to model and optimize system performance
2. Serial Interfaces
   - We are looking for a skilled design engineer to architect and oversee interfacing our low-speed interfaces to our high-speed interconnect
   - These blocks include Boot logic, Serial Interfaces, and debug logic
3. PCIe Interface
   - Working with a small team to implement, debug, and verify a high-performance PCIe interface
   - Build the infrastructure to support PCIe during FPGA emulation and bringup
4. High Speed Cache
   - Working on high performance L2 Cache unit serving the needs of state-of-the art AI processing elements
5. CPU Execution Unit
   - Working on Execution Unit
6. CPU Fetch Unit
   - You will be working on state-of-the-art Fetch Unit architecture design serving both general purpose as well as AI processing element needs.
7. Memory Subsystems
   - Interface and enhancements of an advanced DRAM control block

What You Need for this Position

Verilog / system Verilog / Synthesis / STA / CDC / LINT
Knowledge of C, Scripting (Perl / Shell / Python / AWK) is a plus

1. High Speed Coherent Interconnect
   - Experience with shared-memory and NUMA
   - Experience with high-speed interconnect
   - System performance modelling experience a plus
2. Serial Interfaces
   - Experience with integration and debug of APB, AHB, and AXI interconnects
   - Development of internal logic analyzers and profilers
3. PCIe Interface
   - Experience and background with PCIe controller/device design
   - Familiarity with bus traffic analyzers and logic analyzers
   - Familiarity with data eye and BER analysis
4. High Speed Cache
   - Understanding of high speed and low power processor pipeline designs / ASICs / SoCs and multi-core designs
   - Strong understanding of computer architecture
   - Experience with cache controller designs, understanding of cache coherency protocols, cache hierarchy
   - Logic design experience with state of the art deep submicron technologies specifically low power design techniques
   - Knowledge of ARM and x86 and multicore processor designs is a plus
5. CPU Execution Unit
   - Experience with Arithmetic Unit (ALU) logic design with emphasis on high speed processor pipeline designs
   - Understanding of processor pipeline designs
   - Logic design experience with state of the art deep submicron technologies specifically low power design techniques
6. CPU Fetch Unit
   - Experience with branch prediction algorithms / instruction fetch design of high performance microprocessors
   - Strong understanding of computer architecture
   - Logic design experience with state of the art deep submicron technologies specifically low power design techniques
7. Memory Subsystems
   - Experience with RS and BCH codes
   - Experience with FPGA integration and debug
   - Background in design of DRAM interfaces
   - Logic design experience using Verilog/System Verilog

So if you are a Sr Design Engineer with experience, please apply today!

Applicants must be authorized to work in the U.S.

Job ID: CV5-1770128

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