Design Verification Engineer

Title: Design Verification Engineer

Duration: Full Time

Location: Santa Clara, CA

Description :

Experience in pre-silicon RTL Verification /IP Verification / SOC verification.

Experience in verification domain (block-level, chip-level, and system-level verification) and verification methodologies.

Working knowledge of System Verilog and UVM.

Working Knowledge of simulation models, GLS, Functional and Code Coverage.

Working knowledge on chip protocols: AMBA (AXI, AHB and APB) and Interfaces: PCIe, USB, UART, IPC Experience with using C/C++, PE