Trilyon Inc. is looking for a Senior RTL Design Engineer for its direct client. If you have the skills and experience mentioned below, we would love to discuss it with you.
Role: ASIC/RTL Design Engineer - Senior
Location: San Jose, CA
100% onsite (4 days a week in office, Friday optional)
Top 3 skills: Good understanding of SystemVerilog, analyzing existing designs and making modifications, able to understand tools used by ASIC engineers like Lint, CDC, STA, etc. - scripting is nice to have
KEY RESPONSIBILITIES:
• Write micro-architecture documentation and own major portions of the design and implementation of blocks to meet functional, timing, area, and power requirements.
• Collaborate with architecture and hardware teams to understand the requirements.
• Work with verification and physical design teams to achieve high quality design and successful tape out.
• Design and implement logic functions that enable efficient test and debug.
• Participate in silicon bring-up for features owned.
• Contribute in cross-functional teams to solve novel problems across multiple functional areas in development of required features.
• Implement automation to increase design team efficiency.
PREFERRED EXPERIENCE:
• 5-6+ years' experience
• Must have proven track record of ASIC design on several production tape-outs.
• Experience in Designing RTL block for an SOC.
• Experience in integrating ASIC IP into an SOC.
• Experience with Arm architecture and APB, AXI, CHI protocols.
• Experience with synthesis, static timing analysis & optimizations.
• Experience with design involving Interconnects.
• Experience writing timing constraints and exceptions.
• Experience with automation using scripting techniques such as PERL, Python or Tcl
• Ability to develop clear and concise engineering documentation.
• Experience in Power-saving techniques.
• Ability to organize and present complex technical information.
• Strong verbal and written communication skills
Regards
Nima Nayak | Trilyon, Inc.
Ph: 408-834-7790 Fax: 1-877-896-9866