Design Verification Engineer

Ampcus Inc. is a certified global provider of a broad range of Technology and Business consulting services. We are in search of a highly motivated candidate to join our talented Team.

Job Role: Design Verification Engineer
Work Location: Santa Clara, CA (Onsite Position)
Duration: 6+ Months

Note: UVM/OVM/System Verilog/Python/C/C++

Job Description:

• Architect and create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces.
• Develop test plans and coverage metrics from specifications and writing block and chip-level tests.
• Create PERL/Python scripts to automate creating verification environments, tests generation, and debugging.
• Failure analysis of Register Transfer Level and Gate simulations and resolve them by working with design engineers.
• Create low power test cases using UPF or CPF to verify the desired power intent of the SoC.
• Work with architects to determine the use-case scenarios to simulate.

Preferred Qualifications:

• 7+ years of experience in pre-silicon design verification.
• Proficiency in C-shell scripting, Verilog-HDL & System Verilog.
• Strong knowledge in SV Assertions, UVM/OVM, and functional code coverage.
• SOC Verification experience using ARM Cortex Microcontroller is required.
• Experience with advanced peripheral bus Verification IPs such as GPIO, UART, SPI, SW, JTAG, and I2C.
• Proficient with Cadence tools such as NCVerilog, NCSIM, Simvision. Experience with linting tools (i.e., Spyglass) will be helpful.
• Exposure to SDF annotated simulations with good understanding of parasitic delays and timings is required.
• Exposure to FPGA programming and FPGA tools will be helpful.
• Independent, self-motivated with good analytical & communication skills.

Ampcus is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, protected veterans, or individuals with disabilities.#J-18808-Ljbffr