Analog Layout Engineer

Position Overview:
We are seeking a highly skilled Senior Layout Designer to lead the layout design of high-performance analog cores, including analog-to-digital converters, digital-to-analog converters, PLLs, and transceivers. This role requires expertise in cutting-edge, high-speed CMOS integrated circuits across various advanced foundry process nodes (3nm, 5nm, 7nm, 16nm).
Key Responsibilities:

• Lead the IC layout of high-performance, high-speed CMOS integrated circuits.
• Collaborate with design teams to ensure optimal layout practices and meet project goals.
• Set up and manage LVS, DRC, and ERC environments, troubleshooting and resolving verification issues using Cadence and Mentor tools.
• Conduct floor planning, block-level routing, and top-level chip assembly.
• Implement high-performance analog layout techniques, including common centroid layout, shielding, and thermal-aware layout considerations.
• Ensure designs meet specifications for electromigration and other critical parameters.
• Contribute to the layout of silicon chips for mass production.

Qualifications:

• Experience: 10+ years in high-performance analog layout in advanced CMOS processes.
• Technical Skills:
  • Proficiency in EDA tools from Cadence, Mentor, and Synopsys.
  • Demonstrated experience with analog layout for cutting-edge circuits, especially ADCs, DACs, and PLLs.
  • Familiarity with FinFET process nodes is preferred.
• Design Knowledge:
  • Strong understanding of high-performance analog layout techniques and best practices.
  • Experience with layout automation and skill code is a plus.
• Communication & Teamwork:
  • Excellent written and verbal communication skills.
  • Experience working with distributed design teams is a plus.
• Self-Motivated: Ability to define and adhere to schedules while managing multiple tasks.