Senior Mask Preparation Engineer

Job Description

• Support tape-out work to both internal FABs as well as external foundries.
• Perform DRC & LVS verification on chip design layouts when needed.
• Perform floor-planning for production and development test patterns.
• Write automation scripts for basic layout and/or data prep functions.
• Support Integration team for technology development on new mask layer definition and enablement, metrology and lithography structure introduction.
• Prepare reticle & mask data, collaborating with PDK team on data processing to ensure GR cleanness and data integrity.
• Coordinate QA on reticle data review and release and work with photomask shop vendors on delivery.
• Interface with other engineering teams including Design, Fab, Tech Development as well as mask vendors to facilitate the flow from NPD to manufacturing.

Required Qualifications:

• BS Degree in Electrical/Computer Engineering or related field plus 3+ years of experience.
• Demonstrated programming skills in one or more of the following: SVRF, TCL, C/C++, Java, or Perl/Python.
• Good knowledge of using layout design tools such as Cadence or Mentor.
• Excellent technical communication skills.
• Decent English communication capability.
• Strong learning capability and a good team player.

Preferred Qualifications:

• Familiar with semiconductor manufacturing processes. Basic Process and Device technology experience.
• Demonstrated skills/knowledge of design revision control systems such as Cliosoft, SVN or CVS.
• Advanced EDA flows and tools: Calibre DRV/MDPV, CAT, EBVIEW.
• Experience in FAB operation or process integration is a plus.
• Previous connection with major photomask vendors is a plus.
• Any OPC, RET, MPC/SMO knowledge would be a huge plus.