Company:
TetraMem - Accelerate The World
Location: Fremont
Closing Date: 29/10/2024
Hours: Full Time
Type: Permanent
Job Requirements / Description
Key Responsibilities:
- Write behavioral models for custom analog and mixed-signal circuits in SystemVerilog HDL
- Collaborate with circuit design teams to understand fine details of custom circuits, and with DV teams to craft hooks into the behavioral models for effective verification
- Run various simulations and equivalence checks to ensure that the model matches closely with the custom circuits
- Write scripts and simple tools for automating repetitive tasks
- Review and analyze verification results, and provide feedback to design teams
Requirements:
- B.S. EE and 7+ years of relevant industry experience or equivalent
- Deep understanding of analog and mixed-signal circuit behavior
- Deep knowledge of Verilog/SystemVerilog with ability to write synthesize-able and behavioral code
- Deep knowledge of digital logic gates, clocking and state elements
- Deep knowledge of SPICE simulation, HDL simulation and logic equivalence tools
- Working understanding of analog circuit architecture such as ADC, DAC, LDO, Charge pump etc
- Ability to communicate clearly with multi-functional teams
- Excellent debugging, problem-solving and analytical skills
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TetraMem - Accelerate The World
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