PCIe - DV Engineer

Company:  Mirafra Technologies
Location: Mountain View
Closing Date: 04/11/2024
Hours: Full Time
Type: Permanent
Job Requirements / Description

Need Senior/ Lead Design Verification Engineers for AI acceleration.


Skills: Pcie,HBM, Ethernet, Emulation verification


Min 7+ direct experience in any of -

  • Ethernet mac/pcs VIP integration tests + preferrably network on chip testing.
  • Pcie subsystem VIP integration tests + preferrably embedded risc-v type uP integration tests.
  • HBM subsystem tests.

Emulation infrastructure setup (palladium/protium or zebu).

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Mirafra Technologies
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