Sr. Functional Safety Design & Verification Engineer

Red Oak Technologies is a leading provider of comprehensive resourcing solutions across a variety of industries and sectors including IT, Marketing, Finance, Business Operations, Manufacturing and Engineering. We specialize in quickly acquiring and efficiently matching top-tier professional talent with clients in immediate need of highly skilled contract, permanent or project management based resources.

We are seeking a digital hardware Sr. FPGA/ASIC Design & Verification Engineer. In this role, you are part of the Firmware team and will lead the effort to meet FPGA functional safety certification per the ISO26262 / ASIL-B specification. You should be a hands-on technically savvy individual with a proven track record in FPGA/ASIC design processes with exposure into embedded software development. Ideally, you should have strong experience in all aspects of FPGA subsystems including RTL design, verification and hardware bring up and debug. You should also have an excellent grasp of hardware/software codesign and interface concepts. You should be stickler for details and passionate about reliability and robustness of designs.

Sr. Functional Safety Design & Verification Engineer - FPGA

San Francisco, CA

Responsibilities:

Lead and perform safety analysis of FPGA subsystems

Drive and create functional safety documentation including V model requirements and FMEDA analysis

Define, develop, and integrate features across our FPGA stack with a focus on functional safety and reliability.

Enforce and refine FPGA development process to support functional safety needs.

FPGA development including RTL, simulation, high-speed digital design, DSP algorithm development, verification, synthesis, and timing analysis

Perform hands-on work using laboratory tools for board bring up and troubleshooting

Build automation scripts for repetitive tasks to facilitate efficiency and reliability

Qualifications:

Bachelors in Computer Engineering, Electrical Engineering, or related field

At least 5 years FPGA development experience including HDL code development, simulation, test bench development, synthesis, and timing closure

Experience and understanding of safety concepts and ISO 26262, ASIL-B, or similar standards

Highly proficient with RTL development using Verilog and SystemVerilog

Proficient in some scripting languages such as Python, TCL, Perl, bash

Embedded system development experience in CPU and FPGA based devices such as Xilinx Zynq or Intel Arria devices.

Experience with Xilinx and/or Intel FPGA toolchain.

Experience with DSP algorithm implementations in FPGAs

Experience with processor architectures and various communications protocols such as DDR4, AXI, I2C, UART, SPI, ethernet, etc.

Desirable Qualifications:

Familiar with HLS (High Level Synthesis)

Experience using best practices with version control technologies such as git

Proficient in C or C++ programming language

Familiar with leading verification methodologies like UVM

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