Senior Design Engineer

Sr ASIC/FPGA VHDL Design Engineer – Cardiac Cath Lab _ Camden, NJ _Full-Time(FTE)_Direct Hire

Position: Sr ASIC/FPGA VHDL Design Engineer

Location: Camden, NJ

Base Salary: $115,000 to $140,000 + Best-In-Class Benefits

Security Clearance Required: Yes

Relocation Assistance Available : Yes

Interview Travel Reimbursed : Yes

JD:

• Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed crypto applications. S/he will architect, implement high speed crypto architectures, on ASICs/Xilinx Zynq/MPSOC class FPGAs, with hands on design/debug with Ethernet, TCP/IP protocols.

Essential Functions:

• Responsible for deriving engineering specifications from system requirements and developing detailed architecture
• Execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint)
• Generate test plans
• Perform module level verification, synthesis/STA, Lab debug, SW driven validation on Linux based SOC evaluation boards
• Silicon/FPGA bring up, characterization and production ramp/support/collateral

Qualifications:

• BSEE, MSEE Preferred.
• 5+ year’s equivalent experience developing, implementing, and verification of high-performance communications/networking ASIC/FPGA products.
• Experience mapping algorithms and standards (Ethernet, TCP/IP, AXI) to hardware and architecture/system design tradeoffs.
• Proficient with CDC, RDC. Formal EDA.
• Proficient in VHDL is a must
• Proficient with Synthesis/PAR: SDC, Synopsys Synplify, Vivado
• Strong logic/board debug, and analytical skills.
• Experience with project leadership and EVM
• Active SECRET Clearance

Preferred Additional Skills:

• Proficiency in C++ (OOP)
• Proficiency with Xilinx MPSOC design with writing/debugging with SDKs, BSPs on bare metal/PetaLinux OS.
• Knowledge of PCIe, NVMe, USB protocols.
• Experience with High level synthesis (Xilinx Vivado HLS, AND/OR Mentor Calypto).

Candidate Details:

• 5+ to 7 years experience
• Seniority Level - Mid-Senior
• Minimum Education - Bachelor's Degree
• Willingness to Travel - Never

Screening Questions:

• Do you have an aACTIVE DoD Security Clearance?
• Do you have FPGA experience?
• Do you have VHDL experience?

Ideal Candidate:

• Candidate must have an Active DoD Security Clearance and VHDL experience