Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead MTS Verification Engineer to join our Security team in San Jose/San Francisco, US. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.
As a Lead MTS Verification Engineer, the candidate will be reporting to Sr. Manager Verification Engineering and is a Full-Time position. This engineer will participate in the verification of secure ASIC cores developed by Rambus Security Division (RSD), working with cross functional teams including ASIC design engineers and architects, other verification engineers and system test engineers, security experts, and cryptographers. Cryptography and hardware security experience is not required, but an ability to, and interest in, learning about these areas is important.
Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work.
Responsibilities
- Partner closely with our architecture and design teams in specification and customer requirement reviews
- Design and implement verification test plans, testbenches, infrastructure, and platforms to produce thoroughly verified and robust products
- Implement best verification practices and improve on the existing methodologies and flows
- Tackle sophisticated problems and develop scalable solutions that work across platforms
- Assist with all hardware project phases – bring-up, testing, debug, coverage analysis, and tracking
- Help with IP integration in partner environments and provide debug assistance to customer support teams
Qualifications
- BS or MS degree in electrical or computer engineering or closely related degree strongly preferred; but substantial, relevant, outstanding work experience may substitute in some cases
- Six or more years of experience working as a verification engineer or related field
- Strong written and verbal communication skills: ability to explain complex concepts in front of technical audience
- Strong desire to take ownership of all verification aspects of a project
- Exposure to block-level and/or system-level verification
- High technical competence that includes a track record of effective verification of complex digital designs
- Solid understanding of standard ASIC verification techniques, including:
- Test planning
- Testbench creation
- Code and functional coverage
- Directed and SystemVerilog-based constrained random stimulus generation
- Self-checking – scoreboards, predictors, or reference models
- Assertions
- Solid understanding of verification methodologies (UVM or OVM) and standard testbench languages
- Comfortable with Unix development environments (make, scripting, SVN, etc.)
- Ability to support testbench lint/rule checking, profiling and automation using perl or python scripting
- Familiarity with advanced verification techniques such as object-oriented testbenches and formal verification
- Beneficial Experience:
- Experience developing object-oriented testbench infrastructure in C/C++, OVM, or UVM
- Experience in creating FPGA bitfiles for FPGA emulation/acceleration purposes
- Familiarity with IP integration, IP core delivery, and handoff issues
- Data, software, and/or network security; cryptography
- Ability to work with technical writers in the production of technical documentation
- Personal Attributes:
- Excellent written, verbal, and interpersonal communication skills
- Able to communicate ideas in both technical and user-friendly language
- Able and willing to work in a team-oriented, collaborative environment
- Able to coordinate with internal and external teams across time zones
- A demonstrated ability to prioritize and execute tasks so as to achieve goals in an innovative, fast-paced, and often high-pressure environment
- Proven analytical and creative problem-solving abilities
- Passion for writing clean and neat code that adheres to coding standards