Insight Global is looking for a Sr. R&D Engineer. The consultant needs to work well with cross-functional team members both within our clients’ team and with their customers to meet their SOC development objectives. You will be doing Physical design for SOC verification and chip engineering and implementation. This includes Floor planning, clock insertion, prime time, physical verification, and tape out.
Must Haves:
• 10+ years of related experience
• Fusion Compiler/ICC2
• DC, DCG, DC TOPO
• Flow Development & SOC implementation methodologies that will be deployed and used by our Synopsys customer Physical Design Implementation team members
• Experience with top-level floor planning, bump-maps, RDL IO Pad/Ring creation/verification, power grid creation/verification, hierarchal floor planning/partitioning
• Solid experience with full SOC clocking methodologies (H-Tree, Structure Clocking, MS CTS for Top/Blocks with push/down & bottoms up approaches)
• Highly proficient with SDC STA constraints development driving back-end tools for blocks and full-chip through timing closure & sign-off
• Formality for formal verification (RTL to Gate, Gate-to-Gate) & Formality ECO flows
• Familiar with UPF flows & methodologies for multi-voltage power domains with turn on/turn off using UPF
• ICV for PV (Physical Verification – DRC/ERC/LVS/PERC)
• Ansys Redhawk SC (For IR analysis for static, dynamic, & EMIR )
• Consultants should have a solid track record on execution delivering to high-quality standards for delivering to high quality tape-out