Silicon Verification Engineer 2

Job Title: Hardware Engineering and R&D - Silicon Verification Engineer 2
Duration: 2+ months on W2 (High Chance for Extension)
Location : Fully Remote
Typical Day in the Role
• Purpose of the Team: The purpose of this team is referred to as SCIPS, is to work on digital IP intellectual property and acceleration, including DMA (Direct Memory Access) functions and data compression, decompression, encryption, and decryption. Their digital IPs are integrated into ***'s SoC chip used in Azure Data Centers.
• Key projects: This role will contribute to Accelerator IP.
• Typical task breakdown and operating rhythm: The role will consist of85% : Development, 15% Meetings.
Summary:
The main function of Silicon Verification Engineer is to be a part of the test-plan generation process, creating, testing, and implementing various verification plans.
Job Responsibilities:
• Define, document, and implement a UVM verification environment including agents and scoreboards
• Write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral
• Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes
• Support post-silicon verification activities of the products working with design and product teams
Skills:
• Proficient in using Verilog and VMM/OVM/UVM
• Experience in pre and post silicon verification test flow and automated test benches
• Effective communication, collaboration, and teamwork skills
Education/Experience:
• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related degree required
• 2-4 years of relevant experience required.
Candidate Requirements
• Years of Experience Required: 6+ years of experience in the field.
• Degrees or certifications required: Bachelors degree is required to be eligible for this role.
• Disqualifiers: Candidates with Switching companies often will not be eligible for the role.
• Best vs. Average: The ideal resume would contain UVM,Systems Verilog, Test Bench Development.
• Performance Indicators: Performance will be assessed based on quality of work
Top 3 Hard Skills Required + Years of Experience
1. Minimum 2+years experience with UVM.
2. Minimum 2+ years experience with System Verilog.
3. Minimum 2+ years experience with Test Bench development.