Failure Analysis Engineer

Company:  Adecco
Location: San Jose
Closing Date: 28/10/2024
Hours: Full Time
Type: Permanent
Job Requirements / Description

Are you an Electrical or Test Engineer who loves to travel between the US and Mexico? If so, I have the perfect opportunity for you!


About the Company - Adecco has partnered with an International Electronics Manufacture to hire 7 Full Time/ Direct Hire Failure Analysis Engineer in San Jose, CA or Milwaukee, WI. This company is in Artificial Intelligence (AI) and works with Nvidia. Seeking young engineers who want to grow their careers in AI because they are offering international opportunity to work with cross functional team in AI. Nvidia is competing with TSMC as the main AI chip manufacture.



About the Role - Member of senior engineering team responsible for Product Problem resolution of Industry Standard Servers. Interfaces with customer and The Company R&D, Product Engineering & Quality Engineering organizations to identify elevated factory & field failure symptoms requiring in-depth circuit failure analysis which ultimately leads to identification of root cause, corrective action recommendations of ESSN Server Products portfolio.


ALL EXPENSE PAID Travel Project and then will be stationed in the local plant afterwards. (Either San Jose, CA or Milwaukee, WI )

**Training 2-3 weeks onsite in San Jose, CA or Milwaukee, WI and then travel on an as needed basis to Mexico plant. 5 days training in Taiwan. Must have US passport and open to travel.

**US sponsorship offered for Mandarin speaking candidates

  • Daily Food Stipend for Meals
  • Staying at Hotels in Mexico & Milwaukee
  • Company offer year end bonus
  • Extra pay if working weekends
  • Full Healthcare, Dental, Vision, Retirement Benefits, PTO
  • Must be passport ready to travel



Responsibilities



  • Bachelor's degree in Electrical/Electronic Engineering or a related field is required, along with 3-5 years of experience in the field.
  • Demonstrated ability to debug complex HW issues using logic analyzers, oscilloscopes, and other test equipment.
  • Have experience with electrical and electronic design tools such as CAD, schematic capture tools, and PCB layout software.
  • Additionally, knowledge of various testing methodologies, including functional testing, boundary scan testing, and in-circuit testing is necessary.
  • Working knowledge of key server technologies including Intel and AMD multi-core microprocessors, DDR 3/4 and NAND memory, and PCA design.
  • Must be a self-motivated team player with the ability to work in a customer-oriented, fast-paced, demanding, and often challenging environment with minimal supervision.
  • Knowledgeable in full hardware/software development life cycle.
  • Experience in hardware/firmware/software development and test methodologies.
  • Experience working with internal and external partners.
  • Excellent analytical and problem-solving skills.
  • Willingness to travel abroad to support development of international employees for extended periods of time.


Qualifications - Bachelor's degree in Electrical/Electronic Engineering or a related field is required, along with 3-5 years of experience in the field.


Required Skills - Knowledge of PCI-e protocols, SAS, SCSI, SATA, FibreChannel, Ethernet, WiFi and Bluetooth, NVME, SSD technologies.


Preferred Skills - Experience in hardware/firmware/software development and test methodologies.



Pay range and compensation package -

Failure Analysis Engineer ($85K-$100k). Benefits include Health, Dental, 401K, PTO.

  • Benefit: Health, Dental, 401K, PTO


Equal Opportunity Employer/Veterans/Disabled

  • To read our Candidate Privacy Information Statement, which explains how we will use your information, please navigate to
  • The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:

*The California Fair Chance Act

*Los Angeles City Fair Chance Ordinance

*Los Angeles County Fair Chance Ordinance for Employers

*San Francisco Fair Chance Ordinance

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