RISC-V RTL Design Engineer (Memory Systems & Load-Store)

RISC-V RTL Design Engineer (Memory Systems and Load-Store Architecture)
We are seeking talented engineers specializing in RISC-V RTL design, with a strong focus on memory systems and load-store architecture. As a RISC-V CPU Micro-architecture and RTL Design Engineer, you will work closely with chip architects to define and optimize the micro-architecture, contributing to architecture and product definition throughout the product lifecycle.
Roles and Responsibilities:

• Microarchitecture Development: Lead the exploration and specification of memory systems and load-store architectures for RISC-V CPUs, ensuring efficient data handling and access patterns.
• Performance Exploration: Collaborate with the CPU modeling team to identify and develop high-performance strategies tailored to memory subsystems and load-store operations in RISC-V architectures.
• RTL Ownership: Design, assess, and refine RTL implementations, focusing on optimizing power, performance, area, and timing goals related to memory access and load-store efficiency.
• Functional and Performance Verification Support: Work alongside design verification teams to develop and implement robust functional and performance verification strategies, ensuring RTL designs meet all specifications.
• Design Delivery: Collaborate with cross-functional engineering teams to implement and validate physical design aspects, ensuring timing, area, reliability, and testability align with memory system requirements.

Preferred Qualifications:

• In-depth knowledge of RISC-V microprocessor architecture, specifically related to memory systems and load-store operations.
• Expertise in areas such as cache architecture, memory hierarchy, data prefetching, and memory subsystem optimization.
• Proficiency in RTL design languages such as Verilog, Chisel, and/or VHDL, with experience in simulators and waveform debugging tools.
• Strong understanding of logic design principles, timing, and power implications in the context of memory systems.
• Familiarity with low-power microarchitecture techniques and high-performance strategies for memory access.
• Experience with scripting languages such as Perl or Python for automation and tooling.

Estimated Min Rate : $139000.00
Estimated Max Rate : $234000.00

Note: Any pay ranges displayed are estimations. Actual pay is determined by an applicant's experience, technical expertise, and other qualifications as listed in the job description. All qualified applicants are welcome to apply.

Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

Visit to contact us if you are an individual with a disability and require accommodation in the application process.

For California applicants, qualified applicants with arrest or conviction records will be considered for employment in accordance with the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act. All of the material job duties described in this posting are job duties for which a criminal history may have a direct, adverse, and negative relationship potentially resulting in the withdrawal of a conditional offer of employment.