Senior Design Verification Engineer

Job Title: Sr. Design Verification Engineer

Location: Mountain View, CA

Long Term Contract

What You'll Be Doing:

* Strong PCIe expertise along-with complex SoC debug is must

* At-least 10+ years of experience in System Verilog HVL and C/C++.

* At-least 10+ years of experience in SV/UVM.

* Porting/Testing in FPGA & Emulation (Zebu) Hardware realization Platform is good to have

* Make/Perl/Python

* Ensure customer satisfaction.

* Reporting to customer on daily or weekly progress effectively

What We Are Looking For:

* Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure.

* Verification closure with team

* Ensure customer satisfaction.

* Reporting to customer on daily or weekly progress effectively