ASIC/FPGA Design Verification Engineer

Title: ASIC/FPGA Design Verification Engineer with UVM Experience

Contract Duration: 6 months 1 day

Published: 3 days ago

Responsibilities:

1. Create UVM simulation plan from design specification.
2. Create or modify UVC, Score Board, Monitor, and test cases.
3. Verify until functional coverage and code coverage meet project threshold.
4. Document results.