Principal Engineer, Packaging Engineering

Company Description

At Western Digital, our vision is to power global innovation and push the boundaries of technology to make what you thought was once impossible, possible.

At our core, Western Digital is a company of problem solvers. People achieve extraordinary things given the right technology. For decades, we’ve been doing just that. Our technology helped people put a man on the moon.

We are a key partner to some of the largest and highest growth organizations in the world. From energizing the most competitive gaming platforms to enabling systems to make cities safer and cars smarter and more connected, to powering the data centers behind many of the world’s biggest companies and public cloud, Western Digital is fueling a brighter, smarter future.

Binge-watch any shows, use social media or shop online lately? You’ll find Western Digital supporting the storage infrastructure behind many of these platforms. And, that flash memory card that captures and preserves your most precious moments? That’s us, too.

We offer an expansive portfolio of technologies, storage devices and platforms for business and consumers alike. Our data-centric solutions are comprised of the Western Digital, G-Technology, SanDisk and WD brands.

Today’s exceptional challenges require your unique skills. It’s You & Western Digital. Together, we’re the next BIG thing in data.

As a Packaging Engineer, you will work in the Packaging R&D group on the modeling and simulation, design of experiment, and testing across semiconductor packaging, flash memory product and host levels.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• Responsible for influencing package and product design by addressing the structural integrity and reliability issues in particular and advancing the technology of semiconductor packaging in general. The scope is to address all mechanical aspects of packaging technology and associated material and process interactions. The focus will be on solutions to meet increased demands for small form factor packages with thinner chips, denser interconnects, higher power, and higher reliability (under harsh use conditions such as automotive).
• Responsible for the modeling and simulation, design of experiment, and testing, whichever comes first for best engineering practice, of mechanical responses of IC package and flash products including solid state drives.
• This position will interface with package & product design, electrical and physical characterization, reliability testing, failure analysis, assembly R&D and other process teams.
• Solid background in applied mechanics, especially computational and/or experimental solid mechanics, is required. In-depth knowledge of IC packaging is highly desired.

Qualifications

REQUIRED:

• Ph.D. in Mechanical Engineering plus >3 years, or M.S. in Mechanical Engineering plus >5 years of relevant industrial experience.
• Solid knowledge through academic coursework or experience required in mechanical engineering of IC packaging and related areas.
• Strong background in computational solid mechanics and/or experimental solid mechanics with emphasis on failure analysis and design of experiment.
• Broad knowledge of mechanical behaviors of various material types, including composite laminates, polymers, and metals (e.g., solder).
• Working knowledge in designing and conducting mechanical testing and/or using a commercial FEA package.
• Good understanding of general semiconductor packaging processes, materials, technology and trends, such as substrate design and manufacturing, molding, wire-bonding, die attach, flip chip, TSV, hybrid bonding, etc.

SKILLS:

• Strong oral and written communication skills.
• Demonstrated strong work ethic.
• Ability to work in a global team environment and interact with other engineers to define and implement experiments and conduct relevant simulation for feasibility and validation of concepts and provide design solutions to support new package technology development.