Lead, Microelectronics Packaging Design Engineer

Job Title: Lead, Microelectronics Packaging Design Engineer
Job Code: 16841
Job Location: Palm Bay, FL
Job Schedule: 9/80 (Every other Friday off!)
Relocation: Relocation assistance may be provided to qualified applicants

Job Description:
Responsible for leading the electrical design architecture for microelectronic designs using advanced packaging technology including 3D-ICs, 2.5D, chiplets, silicon interposers, and other applications utilizing high density interconnect. At L3Harris, you will engage with both internal and external customers to define architectures and requirements and then flow down to a design team. You will also engage with leads in the packaging integration team to help define electrical test structures for advanced packaging process technology development. This key role will provide technical insight for our existing technologies and develop new technologies to capture and lead new programs with our military, government, and commercial customers.

Essential Functions:
Define electrical architecture and requirements working with external and internal customers.
Design and layout multilayer structures, lead team to create all necessary design files and documentation for advanced packaging designs.
Perform finite element modeling (FEM) of RF structures using 3D electromagnetic simulation software (HFSS preferred), incorporate analysis results in design structures to optimize performance.
Communicate with process integration team in development runs, provide inputs for electrical test structures to develop architecture
Domestic and International Travel Required up to 25% of time
Qualifications:
Bachelor’s Degree and a minimum of 9 years of prior relevant experience or Graduate Degree and a minimum of 7 years of prior related experience. In lieu of a degree, minimum of 13 years of prior related experience.
Ability to obtain a U.S. government Top Secret/SCI Security Clearance
5+ years experience with advanced microelectronics packaging including through silicon vias, redistribution layers (RDL), chip stacking, and fan out
Experience with silicon layout design flow
Experience using 3D EM simulation, HFSS (preferred)
Preferred Additional Skills:
Experience with Silicon Photonics
Cadence Virtuoso experience is highly preferred
Strong verbal and written communication skills
Ability to lead a design team, size 2-10 people