Hardware Engineering and R&D - Silicon Verification Engineer 2 Silicon Verification Engineer 2

Job Title: Silicon Verification Engineer 2

Job Location: Remote

Job Duration: 2 Months on W2 (with high chances of extension)

Summary:
The main function of the Silicon Verification Engineer is to be a part of the test-plan process, creating, testing, and implementing various verification plans.

Job Responsibilities:

1. Define, document, and implement a UVM verification environment including agents and scoreboards.
2. Write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral.
3. Run tests on RTL and Gate Level Netlists, debug failures to the root cause, and recommend fixes.
4. Support post-silicon verification activities of the products working with design and product teams.

Typical Day in the Role:
The purpose of this team, referred to as SCIPS, is to work on digital IP intellectual property and acceleration, including DMA (Direct Memory Access) functions and data compression, decompression, encryption, and decryption. Their digital IPs are integrated into SoC chips used in Azure Data Centers.

Key projects: This role will contribute to Accelerator IP.

Typical task breakdown and operating rhythm: The role will consist of 85% Development, and 15% Meetings.

Compelling Story & Candidate Value Proposition:
This role provides the opportunity to deliver IP to Azure/AI silicon.

Candidate Requirements:
Years of Experience Required: 5 overall years of experience in the field.
Degrees or certifications required: A bachelor's degree is required to be eligible for this role.
Disqualifiers: Candidates with frequent job switching may not be eligible for the role.
Best vs. Average: The ideal resume would contain UVM, Systems Verilog, and Test Bench Development.

Performance Indicators: Performance will be assessed based on the quality of work.

Skills:
Proficient in using Verilog and VMM/OVM/UVM.
Experience in pre and post-silicon verification test flow and automated test benches.
Effective communication, collaboration, and teamwork skills.

Education/Experience:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related degree required. 2-4 years of relevant experience required.

Top 3 Hard Skills Required + Years of Experience:

1. Minimum 2+ years experience with UVM.
2. Minimum 2+ years experience with System Verilog.
3. Minimum 2+ years experience with Test bench.