JOB TITLE: SOC Emulation Engineer
LOCATION: Santa Clara, CA or Austin, TX
Direct Hire
SALARY RANGE: $150,000 - $180,000
TOP 4 SKILLS:
- In-depth knowledge of digital logic design, CPU/SOC architecture and microarchitecture, and industry standard interfaces and memory subsystems.
- Experienced level knowledge of Verilog/SystemVerilog.
- Experienced level knowledge C/C++. Relevant knowledge of verification methodologies and tools such as simulators, waveform viewers, build and run automation.
- Experience with Palladium, Zebu, Veloce, Protium or HAPS.
In this role, you will help develop Emulation and FPGA based prototyping systems to serve our SOC projects. You will directly work with architecture, design, verification and software/firmware teams to bring up emulation models and develop capabilities that serve various use cases such as functional verification, performance, software/firmware bringup, running realistic workloads, power estimation, hybrid-simulation, and enabling post-silicon debug.
This role may include developing and debugging emulation flows, designing testbenches, monitors or transactors for Emulation or Prototyping, synthesizing the RTL for emulation, and developing RTL collaterals for Emulation.
Responsibilities
- Create and support emulation models from RTL. Drive SOC bringup on emulation platforms, debug test failures and simulation/emulation mismatches.
- Develop compile and runtime flows to support various emulation usage models such as functional verification, hybrid simulation, post-silicon debug, power and software/firmware enablement.
- Develop capabilities to run tests on the emulators and assist in bring-up processes from RTL prototyping through post-silicon validation.
- Work with tool vendors to drive the requirements and resolve any tool issues.
- Drive and contribute to methodology and automation improvements to improve emulation efficiency and value addition.
Requirements
- In-depth knowledge of digital logic design, CPU/SOC architecture and microarchitecture, and industry standard interfaces and memory subsystems.
- Experienced level knowledge of Verilog/SystemVerilog.
- Experienced level knowledge C/C++. Relevant knowledge of verification methodologies and tools such as simulators, waveform viewers, build and run automation.
- Experience with Palladium, Zebu, Veloce, Protium or HAPS.
- Experience with QEmu or other software simulators is a plus.
- Experience in simulation acceleration using transactors or vendors provided accelerated verification IP is a plus.
- Experience in performance analysis/debug techniques.
- Excellent knowledge of one of the scripting languages such as Python, TCL is a plus.
- Excellent skills in problem solving, written and verbal communication, organization skills, and self-motivation.
- Ability to work well in a team and be productive under aggressive schedules.
Education and Experience
- PhD, Master's Degree or Bachelor's Degree in a technical subject area.
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