SerDes Circuit Design Engineering Lead

Company:  Apple
Location: Austin
Closing Date: 10/11/2024
Hours: Full Time
Type: Permanent
Job Requirements / Description

SerDes Circuit Design Engineering LeadAustin,Texas,United StatesHardwareIn this role, you will actively work within and overlook Analog-Mixed/Signal design team and participate in bring-up of embedded circuits; collaborating with many disciplines to enable the world’s premiere products. You will closely work with and lead a talented group of Analog-Mixed/Signal designers working diligently to deliver hard IPs to Apple’s products while exceeding the highest expectations of quality, innovation and efficiency. At Apple, we work every single day to craft products that enrich people’s lives. And in doing so face challenges as SOC/PHY design complexity. If you have strong fundamentals and a track record of tackling technical challenges. If you are passionate about learning new skills and improving the value of your work. If you like to be tuned to the bigger-picture while diving deeply into the details to innovate and tackle problems! We have an opportunity for a forward-thinking and especially hardworking analog mixed signal engineer with background in high speed serial links circuit blocks. As a member of our team with multifaceted strengths, you will have the rare and exciting opportunity to work on upcoming products that will surprise and delight millions of Apple’s customers. And all of this while enjoying a strong culture where you own your career!DescriptionWe have ownership AMS circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, clock generation and distribution, etc.) You will be working with multi-functional teams to define requirements/specs (e.g., modeling, package, board, DFT, ESD, etc.), crafting block-level specifications based on link-budget, behavioral modeling, and transistor-level feasibility. You will also drive mask design to implement layout view of designs. We also are working on Generation/QA of various IP Kit views/files for release to IP consumers, defining production/bench-level testplans, and conducting design reviews of blocks with peers/management to show design meets spec targets and requirements. Work closely with team members to improve methodology and flow.Minimum QualificationsBSEE with 10+ years of proven experience.Previous experience in leading analog and mixed signal teams.Key QualificationsPreferred QualificationsThe ideal candidate should have demonstrated strong leadership experience, in both people management and project driving. Deep understanding of analog mixed-signal design with experience in high-speed serial links.Solid understanding and experience of designing analog mixed signal circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, FiltersIn-depth knowledge of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniquesExperience with Tx/Rx equalization techniques and circuits like de-emphasis, CTLE, DFEExperience with high speed digital circuits (e.g., serializer, deserializer, counters, dividers, etc.)Familiarity with CDR architectures and implementationsDesign experience in advanced CMOS technologies, design with FinFet technologyHands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterizationExperience in lab testing of high-speed serial linksKnowledge of common high-speed SerDes protocols (e.g., PCIe, USB, SATA, etc.)Adept at collaboration with cross functional leaders with strong interpersonal skillsWork closely with team members to improve methodology and flow.MS or PHD preferred.EXPERIENCE IN THE FOLLOWING AREAS IS DESIRABLE:Static timing analysis tools (e.g., Nanotime, Primetime, etc.)Modeling of digitally assisted analog adaptive loops (using C, Matlab or Python, etc.)Able to build VerilogA/AMS behavioral modelsAble to analyze and lead characterization data from lab and volume testingKnowledge of ESD requirementsEducation & ExperienceAdditional RequirementsApple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.Learn more about your EEO rights as an applicant. ( FooterApple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (Opens in a new window) .Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants. United States Department of Labor. Learn more (Opens in a new window) .Apple will consider for employment all qualified applicants with criminal histories in a manner consistent with applicable law. If you’re applying for a position in San Francisco, review the San Francisco Fair Chance Ordinance guidelines (opens in a new window) applicable in your area.Apple participates in the E-Verify program in certain locations as required by law. Learn more about the E-Verify program (Opens in a new window) .Apple is committed to working with and providing reasonable accommodation to applicants with physical and mental disabilities. Reasonable Accommodation and Drug Free Workplace policy Learn more (Opens in a new window) .Apple is a drug-free workplace. Reasonable Accommodation and Drug Free Workplace policy Learn more (Opens in a new window) .

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