ASIC Digital Design Engineer (Low power controller design)

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, and packaging that launch cutting-edge, world-class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

1. Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
2. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
3. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

ASIC Digital Design Engineer (Low power controller design)

Job Description

Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5G's potential into world-changing technologies and products. You will be joining a successful engineering team whose deliveries can be found in billions of mobile, compute and IoT products worldwide.

Based out of Qualcomm's Bangalore office, this role offers a position in Low Power controller IP cores and subsystem digital design targeted for a variety of industry-leading Snapdragon SoCs for mobile, compute, IoT, and Automotive markets.

Key Responsibilities

• Micro-architecture and RTL design for Cores / subsystems related to Low Power controllers.
• Work in close coordination with Systems, Verification, SoC, SW, PD & DFT teams for design convergence.
• Enable SW teams to use HW blocks.
• Qualify designs using static tool checks including Lint, CDC, LEC and CLP.
• Report status and communicate progress against expectations.

Preferred Qualifications

• 5 to 10 years of strong experience in digital front end design (RTL design) for ASICs.
• Expertise in RTL coding in Verilog/SV/VHDL of complex designs with multiple clock domains and multiple power domains.
• Familiar with UPF and power domain crossing.
• Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI.
• Experience in low power design methodology and clock domain crossing designs.
• Experience in Spyglass Lint/CDC checks and waiver creation.
• Experience in formal verification with Cadence LEC.
• Understanding of full RTL to GDS flow to interact with DFT and PD teams.
• Expertise in Perl/TCL/Python language.
• Experienced in database management flows with Clearcase/Clearquest.
• Expertise in post-Si debug is a plus.
• Excellent oral and written communications skills to ensure effective interaction with Engineering Management and team members.
• Team player, self-motivated, should be able to work with minimal supervision.