CPU Microarchitect/RTL Engineer - Execution, Load/Store

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Apple’s Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products, including the iPhone, iPad, Watch, Vision Pro, and Mac. We are looking for an experienced engineer to drive architecture and RTL development of CPU integer, floating-point, and/or load/store execution for our performant cores.

Description

As a CPU Microarchitect/RTL Engineer, you will own or participate in the following:

1. Microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specification.
2. RTL ownership – development, assessment and refinement of RTL design to target power, performance, area and timing goals.
3. Validation - support test bench development and simulation for functional and performance verification.
4. Performance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performance.
5. Design delivery - work with multifunctional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability, and power.

Minimum Qualifications

• Minimum BS and 10+ years of relevant industry experience.
• Knowledge of microprocessor architecture.
• Knowledge of Verilog and/or VHDL.
• Experience with simulators and waveform debugging tools.
• Knowledge of logic design principles along with timing and power implications.

Preferred Qualifications

• Expertise in one or more of the following areas: out-of-order execution, instruction scheduling, integer and floating point execution, load/store execution, cache and memory subsystems.
• Understanding of low power microarchitecture techniques.
• Understanding of high-performance techniques and trade-offs in a CPU microarchitecture.
• Experience in C or C++ programming.
• Experience using an interpretive language such as Perl or Python.

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