Job Description
Insight Global is looking for a Sr. R&D Engineer. The consultant needs to work well with cross-functional team members both within our clients team and with their customers to meet their SOC development objectives. You will be doing Physical design for SOC verification and chip engineering and implementation. This includes Floor planning, clock insertion, prime time, physical verification, and tape out.
Pay rate range: $95 - $103/hr
We are a company committed to creating diverse and inclusive environments where people can bring their full, authentic selves to work every day. We are an equal opportunity/affirmative action employer that believes everyone matters. Qualified candidates will receive consideration for employment regardless of their race, color, ethnicity, religion, sex (including pregnancy), sexual orientation, gender identity and expression, marital status, national origin, ancestry, genetic factors, age, disability, protected veteran status, military or uniformed service member status, or any other status or characteristic protected by applicable laws, regulations, and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or recruiting process, please send a request to (see below) .
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Skills and Requirements
10+ years of related experience
Synopsys Fusion Compiler/ICC2 (Synthesis, DFT insertion, Place & Route, Chip Finishing, PT-SI STA, Timing Closure, PV (DRC/ERC/PERC/LVS)
Synopsys DC, DCG, DC TOPO
Synopsys Flow Development & SOC implementation methodologies that will be deployed and used by our Synopsys customer Physical Design Implementation team members
Experience with top-level floorplanning, bump-maps, RDL IO Pad/Ring creation/verification, power grid creation/verification, hierarchal floorplanning/partitioning
Solid experience with full SOC clocking methodologies (H-Tree, Structure Clocking, MS CTS for Top/Blocks with push/down & bottoms up approaches)
Highly proficient with SDC STA constraints development driving Back End tools for blocks and full-chip through timing closure & sign-off
Synopsys Formality for formal verification (RTL to Gate, Gate-to-Gate) & Formality ECO flows
Familiar with UPF flows & methodologies for multi-voltage power domains with turn on/turn off using UPF
Synopsys ICV for PV (Physical Verification DRC/ERC/LVS/PERC)
Ansys Redhawk SC (For IR analysis for static, dynamic, & EMIR )
Consultants should have a solid track record on execution delivering to high-quality standards for delivering to high quality tape-out o Familiar with Synopsys Lynx a plus
o Ability to define sign-off requirements/margins based on Foundry technology requirements a plus
DFT experience with compression, scan, TDF, and MEMBIST a plus
Experience in PD implementation/design closure on complex IP Sub-Systems such as PCIe, USB, MIPI, DDR, & HBM a plus
Experience with GlobalFoundries, TSMC, & Samsung technology nodes are a plus
RTL Hand-over experience a plus for RTL to GDS null
We are a company committed to creating diverse and inclusive environments where people can bring their full, authentic selves to work every day. We are an equal employment opportunity/affirmative action employer that believes everyone matters. Qualified candidates will receive consideration for employment without regard to race, color, ethnicity, religion,sex (including pregnancy), sexual orientation, gender identity and expression, marital status, national origin, ancestry, genetic factors, age, disability, protected veteran status, military oruniformed service member status, or any other status or characteristic protected by applicable laws, regulations, andordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request to (see below)