Design Verification Engineer

Title: Design Verification Engineer
Location: Burlingame, CA - (Remote) - Candidates in Pacific time zone will be preferred
Type: Contract
Duration: 12+ Months
Note: We are looking for a Design Verification Engineer with 5-15years of relevant experience.
Understanding of Ethernet / project specifications.
Writing Test plan and coverage plan.
Write testcases/scenarios.
Update existing testbench components like generators, drivers, and monitors.
Debug existing tests failing in the regression.
Work on Subsystem and system level verification.
Mandatory:

• 5+ years of proven experience as a DV engineer
• Hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology)
• Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools
• Experience with UPF based simulation flow
• 2+ Years of experience with C/C++
• Tcl and Python (or similar) scripting language

Nice to Have:

• Power and performance FPGA validation
• Python scripting.
• Experience with Power Aware GLS flow
• ASIC design experience
• Experience in formal property verification of complex compute blocks like DSP, CPU or HW accelerators
• Experience with complex SoCs
• Knowledge of coverage merging across simulation and formal