Digital Design Engineering Intern

SenseICs is looking for engineering students for our fall internship cohort! Students should be expected to work 15-30 hours a week on site at our Columbus, Ohio office.

The digital designer is expected to have experience/knowledge with circuit design digital flow from Cadence, Synopsys, or other Computer-aided design (CAD) tools and a working knowledge of analog design principles and signal / power integrity. Their principal tasks include:

• Writing Verilog/VHDL for ASIC or FPGA
• Working with Cadence or equivalent Digital ASIC Tool Suite (such as Genus, Innovus, Tempus, Voltus)
• Working with FPGA design suite (such as Vivado in Xilinx)
• Working with high-level design, simulation, and verification tools
• Scripting in Python, PERL, or other high level languages
• Understanding of Linux OS and command-line interface