Must Haves:
• 4+ years of experience as a Digital Design Engineer.
• Recent experience with IP RTL coding within the past 2-3 years, specifically for ASIC (Per CWAM, anything beyond would be a challenge)
• Experience having worked on a design from scratch – code from the ground up (outline / provide project work, if available)
• Experience in RTL coding and coding for low power in ASICs
• Experience in digital design µArchitecture
• Strong experience with Verilog and SystemVerilog coding
• Perl, Tcl and Python (or similar) scripting experience
• BS Electrical Engineering/Computer Science/Computer Engineering or equivalent experience
Plusses:
• MSEE/CS or equivalent experience
• Experience developing IP for Graphics Processing Unit (GPU), CPU, Compression, or Video ASICs – experience working on coding for these industries (typically aligns with what this team is doing)
• Recent track record of projects where individual coded from ground up that were successfully taped out.
• Former Meta experience
• Former AMD, NVIDIA, Apple, Qualcomm, Intel, Microsoft (on Silicon side) candidates (nice-to-have)
Day-to-Day:
Role Responsibilities (including, but not limited to):
• Own ASIC IP RTL implementation for IP blocks.
• Ensure RTL written meets quality checks like Lint/CDC/RDC.
• Collaborate closely with design team members, technical leads and the architecture team to ensure the block meets the power and performance requirements.
• Collaborate closely with the verification team to develop test plans and review test coverage.
• Perform IP integration
• Supervise the RTL-to-GDS flow and assist with synthesis and timing closure
• Work with FPGA engineers to perform early prototyping
• Support hand-off and integration of blocks into larger SOC environments
• Assist with Algorithm analysis.
Performance Measurement:
Performance is measured based on meeting deadlines by delivering on time while meeting code quality metrics and DV quality metrics.
Role Mandate:
The team is responsible for doing digital design for graphics IP and is looking for an individual to collaborate on uarchitecture development and perform RTL coding on the next version of our IP. This individual will have the opportunity to work on block design implementation for an IP that is going into future AR products.