Principal Design For Test (DFT) Engineer

at indie Semiconductor

San Jose

Overview

Do you enjoy working in a creative fast-growing entrepreneurial environment? With indie you´ll never walk alone! We place high value on our teams and pursue excellence for our employees and customers!

indie is empowering the Autotech revolution with next generation automotive semiconductors and software platforms. We focus on edge sensors spanning multiple modalities including LiDAR, radar, ultrasound and vision for Advanced Driver Assistance Systems (ADAS), autonomous vehicles, connected car, user experience and electrification applications.

The Vision business unit is responsible for creating power-efficient System-on-a-Chip (SoC) ASIC devices for the automotive market.

Responsibilities

1. Architect, implement, and deploy DFT flow for ASICs designed by the Vision BU.
2. Drive the entire DFT cycle of the ASIC including but not limited to test insertion, test coverage assessment, and at-speed testing, accompanied by implementation knowledge of test pattern development, scan compression, JTAG, IJTAG, Memory BIST and Logic BIST.
3. Lead effort in fault simulation including debug and verification.
4. Taking new silicon into volume production.
5. Ability to step in and help with debugging of existing post-production ASICs.
6. Architect re-usable DFT strategies that can be used across generations of similar ASICs and possible different packaging options.
7. Interact with members of different teams like Design, Software, and Product to ensure successful deployment and support of DFT features in the ASIC.

Requirements

1. 10+ years (Bachelor's + 10 years, Master + 5 years) of complete lifecycle experience with multiple ASICs
2. Demonstrated experience in industry standard DFT tools and methodology. Knowledge of Mentor test-tool suite a plus.
3. Be involved in synthesis of DFT features and structures. Assist in logical equivalence check between pre and post DFT netlists.
4. Create and/or modify to propagate DFT constraints for in-house and external IP and be knowledgeable with regards to DFT related Static Timing Analysis.
5. Knowledge of automation tools and scripting languages like TCL, Perl, Python etc.
6. Ability to debug DFT related issues in simulation and up to post-silicon bring-up and post-production phases.
7. Be a team player and exhibit proactive approach to design, debug, and problem solving
8. Good written and verbal communication skills

indie Semiconductor and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.