Job Description: Top 5 Required Skills (These are not preferred skills. If the candidate does not have these require skills, they will be rejected completely)
1) Silicon debug on Bench platform for test and characterization of industry standard SerDes Interfaces like Ethernet/PCIe/USB4/USB3/UFS/MIPI.
***SerDes is a must****
2) Familiarity with SERDES Transmitter and Receiver design blocks, High Speed Analog/Digital Circuits, VLSI, semiconductor physics
3) Familiarity with concepts in Power Integrity, Signal Integrity, Jitter Analysis, equalization techniques (CTLE/DFE).
4) Hands on experience with lab equipment such as Oscilloscopes, J-BERT, TDRs, VNAs.
5) Familiarity with Board Design concepts(Schematic reviews, Layout best practices etc)
Technologies: that this person must have to perform the required job duties (These are not preferred technologies - If they do not have these technologies they will be rejected completely)
- Experience with Python/C# for test automation.
- Strong interpersonal, problem solving & Silicon debugging skills.
Required Education: (Candidates without this level will be rejected completely):
5 + years experience with a Bachelor's degree in Computer Science, Engineering, Information Systems
-OR-
3+ years experience with Master's degree in Computer Science, Engineering, Information Systems
Physical Requirements: if any:
-None
Key Words: (Completed by TAPFIN During Intake Call):
SerDes Test
Silicon Debug
HSIO Char
PCIe Test
USB Test
Compliance Test
Silicon Characterization
Job Description:
This position is for the Post Silicon Test and characterization of highly integrated SOCs ( System on Chip) designed by Qualcomm. The preferred candidate would be someone with experience in SERDES test and characterization on the bench platform. Main responsibilities includes developing test and debugging silicon to characterize High Speed SERDES Interfaces such as Ethernet, PCIe, USB3, UFS,DP, MIPI(DSI,CSI), PLLs and leading edge LP-DDR & PC-DDR Subsystem components (DRAM, DRAM Controller, PHY, IOs, Clocking architecture, Delay circuits, Power Distribution Network) as well as other proprietary interfaces . Responsibilities includes developing and executing characterization plans for High Speed Serial interfaces, optimize analog front end parameters, compliance testing and validation, supporting first silicon bring up & debug. You will also assist in HW design and debug power integrity (PI) and signal integrity(SI) issues related to package and board design. You will work closely with the design team for chip/circuit bring up and debug. You will work closely with Application Engineering teams to resolve customer issues/RMA debug in a time critical environment.
Comments for Suppliers: Submit top 3 candidates only!
*Do not submit any candidates previously submitted to Request #5015313-1 - Engineer
How many rounds of interviews should be expected? 2
Work Location: San Diego Lab AQ-254, in the lab presence required all five days initially and at least 3 days a week after getting fully acquainted with hardware and software setup of the lab.
Shift: Hour/Days of Work; regular day time office hours.