Senior Staff RTL Verification Engineer

Team Overview:

We are looking for a Senior Staff RTL Verification Engineer to join the Impinj silicon engineering team to work on the next generation of tag and reader chips. We are a fun, hardworking team of top-tier silicon designers that value and celebrate partnership and collaboration.

What you’ll do:

• Work on multiple aspects of tag endpoint and reader chip designs including C behavioral model development, RTL model coding, debug, verification coverage improvement through directed Verilog Test Bench development, writing System Verilog assertions and coverage monitors, writing test plans for features and functional blocks in the endpoint ICs and reader IC microarchitectures. Writing directed tests and pseudo random tests that deliver comprehensive functional coverage.
• Collaborate closely with a cross-functional team of logic designers, analog designers, test engineers, systems engineers through all phases of product development to deliver new features and products to market.
• Evolve existing RAIN RFID (Radio Frequency Identification) products through feature enhancements and performance improvements.
• Participate in design and verification of ultra-low power silicon chips (power measured in nano Watts) that are produced in the billions per year.
• Take on a technical leadership role, mentor junior engineers, and help to grow the RTL verification team.

What you’ll bring:

• BS in Computer Engineering or Electrical Engineering with coursework in computer architecture.
• Basic knowledge of a micro-controller micro architecture.
• 8-10 years of RTL model verification experience.
• Experienced in the development of C and system C behavioral models.
• Proficient coding skills and experience with System Verilog.
• Experience with SV assertion development and use of SV assertions for functional coverage.
• Experience writing directed tests and constrained pseudo random tests.
• Experience developing UVM re-usable sequences and coverage monitors.
• Experience with Universal Verification Methodology.
• Experience using different code coverage tools.
• Experience testing complex finite state machines.
• Ability to take protocol, functional, and feature specifications and create/document an efficient test plan.
• Experience in developing and implementing RTL verification test plans.
• Proficiency in scripting languages Perl, Ruby or Python and Unix shell scripts.
• Experience developing system level architectural checker.
• Experience bringing designs from concept through tape-out and to market.
• Excellent written and verbal communication skills.
• Demonstrated mentoring skills.

Compensation and Benefits:

The benefits listed below may vary depending on the nature of your employment with Impinj and the country where you work.

The typical base pay range for this role across the US is $135,000 - $208,000. Individual base pay depends on various factors such as complexity and responsibility of role, job duties, requirements, and relevant experience and skills. Both market wage data and the mid-point of the pay range is reviewed and used as the starting point for all new hire offers. Offers are made within the base pay range applicable at the time.

At Impinj, certain roles are eligible for additional rewards, including merit increases, annual bonuses, and stock. These awards are allocated based on individual performance. In addition, certain roles also have the opportunity to earn sales incentives based on revenue or utilization, depending on the terms of the plan and the employee’s role. US-based employees have access to healthcare benefits, a 401(k) plan and company match, among others.

For a more comprehensive list of US employment benefits, click here .