Design Verification Engineer

Company:  Acceler8 Talent
Location: Mountain View
Closing Date: 05/11/2024
Hours: Full Time
Type: Permanent
Job Requirements / Description

Acceler8 Talent has recently partnered with a company that is redefining AI hardware, focusing on maximizing performance for large language models (LLMs) like GPT. With a commitment to cost efficiency and optimizing performance-per-dollar, their technology offers competitive latency and low-level hardware control. Their scalable hardware enables faster model development and accessibility for researchers and startups.


Founded by two previous leaders of a FAANG company, they are leading the charge as the compute platform for AGI, crafting comprehensive solutions from silicon to systems.


They are actively looking for a strong Design Verification Engineer, someone who is ready to shake up the world that is AI.


Responsibilities:


You will Contribute to their verification methodology with a scalable solution across blocks, subsystems, fullchip and system-level validation and you will own portions of verification execution at subsystem and chip-level and create testbenches, tests and related artifacts to achieve structural and functional coverage closure.


Requirements:

  • Concept-to-silicon experience in driving verification from an architecture and/or design specification to production silicon
  • Experience with SystemVerilog, Python, C/C++, Bluespec and similar scripting and programming languages for verification and silicon modeling
  • Production experience with advanced verification methodologies such as UVM, assertion-based verification (AVB), formal verification, etc.
  • Production experience with creating portable tests and drivers for verification that apply to silicon validation and post-silicon debug
  • Strong understanding of silicon micro-architecture and design concepts used in high-performance compute (CPUs, GPUs, accelerators), high-speed connectivity, memory management and related functionalities
  • Familiarity with emulation and prototyping platforms and methodologies is a plus
  • Hands-on experience with participation in silicon debug and bring-up is a plus


If interested in joining them please apply here or reach out to

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