Hi
Hope you are doing good.
We are looking for RTL Design Engineer. This is a contract position. Please check the job description and reply to me if you are available for this position.
Title: RTL Design Engineer
Location: Bay Area, CA (Day 1 Onsite)
Duration: 6 Months
Candidate Roles and Responsibilities
• Collaboration with offshore team.
• IC role and offshore task coordination
• Must have 10+ years of experience with ASIC design activities - Verilog RTL, testcase debug, netlist checks, CDC checks, coverage analysis, timing closure, x-prop/gate level simulations.
Preferred:
• Domain knowledge in PCIE/CXL, DDR, AMBA AXI/APB protocols.
Thanks and Regards,
Manish Kumar
P: 972-430-7053 Email:
Linkedin: linkedin.com/in/manishtechie14
Suite # 660 1320 Greenway Drive, Irving, TX 75038
Website: