Principal Engineer Packaging Engineering

Job Description

As a Packaging Engineer, you will work in the Packaging R&D group on the modeling and simulation, design of experiment, and testing across semiconductor packaging, flash memory product and host levels.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

1. Responsible for influencing package and product design by addressing the structural integrity and reliability issues in particular and advancing the technology of semiconductor packaging in general. The scope is to address all mechanical aspects of packaging technology and associated material and process interactions. The focus will be on solutions to meet increased demands for small form factor packages with thinner chips, denser interconnects, higher power, and higher reliability (under harsh use conditions such as automotive).
2. Responsible for the modeling and simulation, design of experiment, and testing, whichever comes first for best engineering practice, of mechanical responses of IC package and flash products including solid state drives.
3. This position will interface with package & product design, electrical and physical characterization, reliability testing, failure analysis, assembly R&D and other process teams.
4. Solid background in applied mechanics, especially computational and/or experimental solid mechanics, is required. In-depth knowledge of IC packaging is highly desired.

Qualifications:

REQUIRED:

1. Ph.D. in Mechanical Engineering plus >3 years, or M.S. in Mechanical Engineering plus >5 years of relevant industrial experience.
2. Solid knowledge through academic coursework or experience required in mechanical engineering of IC packaging and related areas.
3. Strong background in computational solid mechanics and/or experimental solid mechanics with emphasis on failure analysis and design of experiment.
4. Broad knowledge of mechanical behaviors of various material types, including composite laminates, polymers, and metals (e.g., solder).
5. Working knowledge in designing and conducting mechanical testing and/or using a commercial FEA package.
6. Good understanding of general semiconductor packaging processes, materials, technology and trends, such as substrate design and manufacturing, molding, wire-bonding, die attach, flip chip, TSV, hybrid bonding, etc.

SKILLS:

1. Strong oral and written communication skills.
2. Demonstrated strong work ethic.
3. Ability to work in a global team environment and interact with other engineers to define and implement experiments and conduct relevant simulation for feasibility and validation of concepts and provide design solutions to support new package technology development.

Additional Information

Western Digital is committed to providing equal opportunities to all applicants and employees and will not discriminate based on their race, color, ancestry, religion, sex, gender, age, national origin, sexual orientation, medical condition, marital status, physical or mental disability, genetic information, or other legally protected characteristics. We also prohibit harassment of any individual on any of the characteristics listed above.

Western Digital thrives on the power and potential of diversity. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect, and contribution.

Western Digital is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at to advise us of your accommodation request.