Digital Design Engineer for Power Management ASICs

Company:

Qualcomm Global Trading Pte. Ltd.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

Minimum Qualifications:

1. Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
2. OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
3. OR PhD in Science, Engineering, or related field.

Job Description:

Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5G's potential into world-changing technologies and products. This is the Invention Age and this is where you come in.

Digital Design Engineer for Mixed-Signals IPs, ASICs and Chipsets used in Qualcomm Snapdragon power solutions. IPs include telemetry ADCs, 100W+ charging (Quick Charge 5.0), 5G power (mmW, envelope tracking, high performance low noise oscillators etc…) and high efficiency power management (DC-DC charge pumps, bucks and linear regulators).

* Work includes partnering with international teams in all stages of development from system definition to high-volume (100M+) OEM launches.

* Successful applicants will be responsible for participating in, or leading, the design of state-of-the-art Mixed-Signals ASICs in advanced digital deep sub-micron CMOS processes for multi-function mobile platforms.

* Responsibilities will include all, or some, of the following:

1. Micro-architecture of chipset, chip and IP-level designs (designs include firmware, RTL and analog hard macros)
2. Negotiating and executing System specification and requirements
3. Actively involved in all aspects of the front-end design from Architecture definition/RTL development/Simulation/Synthesis/DFT Insertion/Static Timing closure and closely work with the Place and Route function.
4. Document ASIC development, hold detailed design reviews with cross-functional teams, generate and maintain design schedules.

Preferred Qualifications:

1. MS+2 Years ASIC design, verification, or related work experience
2. Applicants should have sound digital design principles with exposure to Front-end Digital design tools – HDL, RTL Linting, CDC, Synthesis, BIST/SCAN insertion, STA.
3. Strong communication and organizational skills
4. Strong process-oriented mindset.