5529 Jobs Found for Rebecca Myers Design Llc in San Jose
Role: ASIC/RTL Design Engineer Location: San Jose, CA – 95101 Duration: 12 months Top 3 skills: Good understanding of System Verilog, analyzing existing designs and making modifications, able to understand tools used by ASIC engineers like Lint, CDC, STA, etc. - scripting is nice to have KEY RESPONSIBILITIES: Write micro-architecture documenta...
Responsibilities: IP and/or chip level micro-architectures, implementation, and validation Develop algorithmic computation engines, NAND memory controller, and so on Write up micro-architecture and design document and be able to present to customers Develop RTL, perform synthesis, lint and CDC check Working with customers to trouble shooting,...
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.The Cadence Silicon Solution Group (SSG) develops industry leading IPs that enable our customers in a variety of markets - from the endpoint to the edge to the cloud and AI for SoC and chiplets. At Cadence we’re helping set the standard on I...
Xconn-technologies Inc is a Silicon Valley based company working on the world’s leading edge PCIe & CXL Switch for AI/ML & Data center applications. Xconn-technologies is seeking a highly motivated & Passionate Principal design engineer to lead a PCIe/CXL switch subsystem design. Job Description: As a Principal ASIC design engineer, you will lea...
Job Title : Senior ASIC Physical Design Engineer Job Location: Santa Clara, CA (Hybrid) Key Responsibilities Chip level floor planning, partitioning, timing budget generation, power planning, top-level PnR, CTS, block integration and ECO generation. Expertise in timing closure (STA) of high frequency blocks Handling blocks of high instance coun...
Job Title : Senior ASIC Physical Design Engineer Job Location: Santa Clara, CA (Hybrid) Job Description: The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip development, executing from the inception of the design (RTL or gate netlist) through the tape-out release to wafer fabrication using the latest S...
Job Description: As a Principal ASIC design engineer, you will lead a part of innovative & advanced design of PCIe & CXL switches for HPC, AI/ML & Data centers. Your primary job is to work closely with architecture team to write micro-architecture specifications from an architecture spec. The job also includes RTL design & helping the design verif...
Position Summary: We are seeking a highly skilled RTL Designer with experience in domains such as PCIe, NVMe, and ability to read 3rd party RTL. The ideal candidate will have a background in working with companies that develop SOC. This position requires working on-site for one of our clients in San Jose, California. Responsibilities: Develop and...
Position can be worked from Pleasanton, CA office or San Jose, CA office RESPONSIBILITIES Participate in defining chip architecture by analyzing competitors' flash operations and developing proprietary flash design technologies to meet marketing-defined specifications. Design analog circuits, including charge pumps, reference voltage generators, ...
Job Title: Sr. IC Design Engineer //Sr. Integrated circuit Design Engineer Work Location: San Jose, CA (Onsite) Employment Type: Full Time-Permanent Job Description: As the market leading innovator in energy efficient power conversion, Our client is seeking Sr. Staff IC Design Engineer at our San Jose location. Having pioneered many new power ...