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46 Jobs Found for Casey Industrial in San Jose
It’s an exciting time to be at Infoblox. Named a Top 25 Cyber Security Company by The Software Report and one of Inc. magazine’s Best Workplaces for 2020, Infoblox is the leader in cloud-first networking and security services. Our solutions empower organizations to take full advantage of the cloud to deliver network experiences that are inherently ...
Role – Hardware Design Engineer (High Speed) Location : San Jose, CA (100% Onsite) Hire Type : Full Time Description - External Job description: Hardware Engineer- Strong lab skills with measurement experience (VNA, TDR, Real Time/Sampling Scopes, BERT, SSA). BS or MS degree in Electrical or Computer Engineering (EE / CE) and Minimum of 5 year...
Job Title : Senior ASIC Physical Design Engineer Job Location: Santa Clara, CA (Hybrid) Key Responsibilities Chip level floor planning, partitioning, timing budget generation, power planning, top-level PnR, CTS, block integration and ECO generation. Expertise in timing closure (STA) of high frequency blocks Handling blocks of high instance coun...
Role – Hardware Design Engineer (High Speed) Location : San Jose, CA (100% Onsite) Hire Type : Full Time Description - External Job description: Hardware Engineer- Strong lab skills with measurement experience (VNA, TDR, Real Time/Sampling Scopes, BERT, SSA). BS or MS degree in Electrical or Computer Engineering (EE / CE) and Minimum of 4-6 year...
Job Description: Are you obsessed with data, partner success, taking action, and changing the game? If you have a whole lot of hustle and a touch of nerd, come work with Pattern! We want you to use your skills to push one of the fastest-growing companies in the US to the top of the list. Pattern is the premier partner for global ecommerce accelera...
Job Title : Senior ASIC Physical Design Engineer Job Location: Santa Clara, CA (Hybrid) Job Description: The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip development, executing from the inception of the design (RTL or gate netlist) through the tape-out release to wafer fabrication using the latest S...