Optimize Recruitment Jobs in Santa Clara October 2024

Unleash your creativity with design and creative job opportunities! Whether you're a graphic designer, UX/UI specialist, animator, or art director, our platform showcases roles in leading agencies, studios, and tech companies. Join us today to turn your passion into a fulfilling career in design and creative fields!

125 Jobs Found for Optimize Recruitment in Santa Clara

£125 - £150 Per Annum

Responsibilities About UsTikTok is the leading destination for short-form mobile video. At TikTok, our mission is to inspire creativity and bring joy. TikTok's global headquarters are in Los Angeles and Singapore, and its offices include New York, London, Dublin, Paris, Berlin, Dubai, Jakarta, Seoul, and Tokyo.Why Join UsCreation is the core of Tik...

Position- Mixed Signal DV Engineer Location- Sunnyvale CA - Onsite role Job description: We are seeking Mixed signal Design Verification Engineer who is proficient in system verilog real number modeling and experience with UVM. Proficient in debug skills and experienced with gate level parasitic annotated simulations. Candidate should be availab...

Job Title : Senior ASIC Physical Design Engineer Job Location: Santa Clara, CA (Hybrid) Key Responsibilities Chip level floor planning, partitioning, timing budget generation, power planning, top-level PnR, CTS, block integration and ECO generation. Expertise in timing closure (STA) of high frequency blocks Handling blocks of high instance coun...

Role – Hardware Design Engineer (High Speed) Location : San Jose, CA (100% Onsite) Hire Type : Full Time Description - External Job description: Hardware Engineer- Strong lab skills with measurement experience (VNA, TDR, Real Time/Sampling Scopes, BERT, SSA). BS or MS degree in Electrical or Computer Engineering (EE / CE) and Minimum of 4-6 year...

Job Title : Senior ASIC Physical Design Engineer Job Location: Santa Clara, CA (Hybrid) Job Description: The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip development, executing from the inception of the design (RTL or gate netlist) through the tape-out release to wafer fabrication using the latest S...

An error has occurred. This application may no longer respond until reloaded. Reload 🗙