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136 Jobs Found for Moonshot Ai in Santa Clara
Position- Mixed Signal DV Engineer Location- Sunnyvale CA - Onsite role Job description: We are seeking Mixed signal Design Verification Engineer who is proficient in system verilog real number modeling and experience with UVM. Proficient in debug skills and experienced with gate level parasitic annotated simulations. Candidate should be availab...
DescriptionAmazon Web Services (AWS) is the world’s most comprehensive and broadly adopted cloud platform, offering over 200 fully featured services from data centers globally. Millions of customers—including the fastest-growing startups, largest enterprises, and leading government agencies—are using AWS to lower costs, become more agile, and innov...
Job Title : Senior ASIC Physical Design Engineer Job Location: Santa Clara, CA (Hybrid) Key Responsibilities Chip level floor planning, partitioning, timing budget generation, power planning, top-level PnR, CTS, block integration and ECO generation. Expertise in timing closure (STA) of high frequency blocks Handling blocks of high instance coun...
Job Title : Senior ASIC Physical Design Engineer Job Location: Santa Clara, CA (Hybrid) Key Responsibilities Chip level floor planning, partitioning, timing budget generation, power planning, top-level PnR, CTS, block integration and ECO generation. Expertise in timing closure (STA) of high frequency blocks Handling blocks of high instance coun...
Role – Hardware Design Engineer (High Speed) Location : San Jose, CA (100% Onsite) Hire Type : Full Time Description - External Job description: Hardware Engineer- Strong lab skills with measurement experience (VNA, TDR, Real Time/Sampling Scopes, BERT, SSA). BS or MS degree in Electrical or Computer Engineering (EE / CE) and Minimum of 4-6 year...
Job Title : Senior ASIC Physical Design Engineer Job Location: Santa Clara, CA (Hybrid) Job Description: The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip development, executing from the inception of the design (RTL or gate netlist) through the tape-out release to wafer fabrication using the latest S...