Ineos Automotive Jobs in Sunnyvale October 2024

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26 Jobs Found for Ineos Automotive in Sunnyvale

£150 - £200 Per Annum

Job Details: Job Description: Do Something Wonderful! Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because a...

Position- Mixed Signal DV Engineer Location- Sunnyvale CA - Onsite role Job description: We are seeking Mixed signal Design Verification Engineer who is proficient in system verilog real number modeling and experience with UVM. Proficient in debug skills and experienced with gate level parasitic annotated simulations. Candidate should be availab...

Position- Mixed Signal DV Engineer Location- Sunnyvale CA - Onsite role Job description: We are seeking Mixed signal Design Verification Engineer who is proficient in system verilog real number modeling and experience with UVM. Proficient in debug skills and experienced with gate level parasitic annotated simulations. Candidate should be availab...

Job Title : Senior ASIC Physical Design Engineer Job Location: Santa Clara, CA (Hybrid) Key Responsibilities Chip level floor planning, partitioning, timing budget generation, power planning, top-level PnR, CTS, block integration and ECO generation. Expertise in timing closure (STA) of high frequency blocks Handling blocks of high instance coun...

Job Title : Senior ASIC Physical Design Engineer Job Location: Santa Clara, CA (Hybrid) Key Responsibilities Chip level floor planning, partitioning, timing budget generation, power planning, top-level PnR, CTS, block integration and ECO generation. Expertise in timing closure (STA) of high frequency blocks Handling blocks of high instance coun...

Job Title : Senior ASIC Physical Design Engineer Job Location: Santa Clara, CA (Hybrid) Job Description: The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip development, executing from the inception of the design (RTL or gate netlist) through the tape-out release to wafer fabrication using the latest S...

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