Sv Tech Systems Jobs in San Jose October 2024

We are seeking an experienced engineer focused on PCIe & IO Subsystem design for high-performance CPUs. This role involves working on a server-class SoC and can be based out of Austin, TX; Santa Clara, CA; Boston, MA; or Toronto, Ontario. Responsibilities: Design and development of the PCIe/IO subsystem unit for a high-performance CPU SoC from scr...

Job Description Are you interested in quantum imaging? Join us! In this role you can apply your expertise in Front End Digital design for ASICs driving our latest sensors – highlighted by their low read noise capabilities. This involves architecting and implementing digital functions of sensors and validating the products through programming the ...

Preferred Experience Excellent track record in designing IP's, Subsystems involving CPUs, bus interconnects. Working experience on Fetch Unit, MMU/IO-MMU, Load-Store, RISCV-Privilege Architecture, Advance Interrupt Architecture. Worked with IP's or Subsystem involving CPUs like RISC-V, ARM or x86 is a big plus. Knowledge of computer ar...

PFA JD for DV lead Eng SV UVM - Subsystem and Full chip level. SOC / subsystem/ IP /module level verifications from spec to silicon bring up Experience of working closely with backend team for timing closure Experience with constrained, random, C based Processor, GLS, Low power, Assertions based verifications. Custom Clocking experience, under...

Position Title : Sr ASIC Design Verification Engineer Location: San Jose CA ( Onsite ) Status: US Citizenship / Permanent Resident required. As a member of the development team, you would implement and execute SV/UVM based Verification environments. Projects involve Verification of custom logic blocks as well as the Verification of the “full chip...

Provide design verification services for our PCIe/CXL Switch SoCs Responsibilities Test bench development using System Verilog and UVM Test plan and test case development Experience in developing SV Functional coverage models and SVA assertions and cover properties Regression setup and debug RTL level and gate level simulations working with desig...

ASIC Design Verification Engineer (PCIe/CXL Switch SoCs) San Jose, CAFull-time + BenefitsUS Citizen or US Permanent ResidentResponsibilities: • Test bench development using SystemVerilog and UVM• Test plan and test case development • Experience in developing SV Functional coverage models and SVA assertions and cover properties• Regression setup and...

Provide design verification services for our PCIe/CXL Switch SoCs ​ Responsibilities Test bench development using System Verilog and UVM Test plan and test case development Experience in developing SV Functional coverage models and SVA assertions and cover properties Regression setup and debug RTL level and gate level simulations working with des...

ASIC Design Verification Engineer (PCIe/CXL Switch SoCs) Full-time San Jose, CA US Citizen or US Permanent Resident Responsibilities: Test bench development using SystemVerilog and UVM Test plan and test case development Experience in developing SV Functional coverage models and SVA assertions and cover properties Regression setup and debug RTL l...

Position: CPU RTL Design Engineer, Location: San Jose, CA (Onsite/Remote) Job Description: Design and develop IP's, Subsystems, SOC integration. Develop CPU subsystem front-end designs, emphasizing on microarchitecture and RTL design for the next generation CPU. Microarchitecture development and specification - From early high-level architectura...