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44 Jobs Found for Gate Sentry in Santa Clara
6 to 10 years of experience in DV. Testbench development – System Verilog Universal Methodology (“UVM”), Python, and C tests Integration/development of C tests/Application Programming Interface (“APIs”) and software build flow. Integration of UVM testbenches. Test development and debug, including without limitation tests for functionality, power, p...
6 to 10 years of experience in DV. Testbench development – System Verilog Universal Methodology (“UVM”), Python, and C tests Integration/development of C tests/Application Programming Interface (“APIs”) and software build flow. Integration of UVM testbenches. Test development and debug, including without limitation tests for functionality, power, p...
Senior Physical Design Engineer
Posted 19 Sep 2024Job Description: Responsible for doing all aspects of SOC Physical Design implementation. For this position, the candidate will be representing Synopsys under our Design Services organization working on physical design implementation for SOC programs our customers have contracted to Synopsys. Some programs can be working with Synopsys team members ...
Job Description: Responsible for doing all aspects of SOC Physical Design implementation. For this position, the candidate will be representing Synopsys under our Design Services organization working on physical design implementation for SOC programs our customers have contracted to Synopsys. Some programs can be working with Synopsys team members ...
The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yi...
The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yi...
8+years of hands-on Verilog programming experience for ASIC, with proficiency in front-end Cadence tools and methodologies, along with a demonstrable track record of delivering complex RTL logic designs for multi-million gate high speed processors/ASICs. Knowledge of high speed compute (e.g. floating point vector processing units (VPU), GPU shader ...
8+years of hands-on Verilog programming experience for ASIC, with proficiency in front-end Cadence tools and methodologies, along with a demonstrable track record of delivering complex RTL logic designs for multi-million gate high speed processors/ASICs. Knowledge of high speed compute (e.g. floating point vector processing units (VPU), GPU shader ...
8+years of hands-on Verilog programming experience for ASIC, with proficiency in front-end Cadence tools and methodologies, along with a demonstrable track record of delivering complex RTL logic designs for multi-million gate high speed processors/ASICs. Knowledge of high speed compute (e.g. floating point vector processing units (VPU), GPU shader ...
Apple's growing wireless silicon development team is developing the next generation of wireless silicon! In this role, you'll be responsible for ASIC pre-silicon verification of extremely complex high throughput communication systems. You will develop leading-edge testbenches, enhance advanced methodologies, develop verification plans, debug functi...