149 Jobs Found for Gate Sentry in Santa Clara
The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yi...
The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yi...
Responsibilities: Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them. Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive...
Responsibilities: Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them. Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive...
Minimum Requirements: Requires Bachelor’s degree or its equivalent in the field(s) of Electronics and Telecommunications or related field. Location: Calsoft Labs Inc., d/b/a ACL Digital - 2890 Zanker Road, Suite 200, San Jose, CA 95134 Experience: BS 5 + years Knowledge of verification methodology involving OOPs concepts C++, OVM/UVM. Design and ...
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The intern will do research of advanced gate modeling for timing analysis and library characterization.Position Requirements Solid knowledge of digital circuits, skillset to run circuit simulations, collecting and processing results using s...
8+years of hands-on Verilog programming experience for ASIC, with proficiency in front-end Cadence tools and methodologies, along with a demonstrable track record of delivering complex RTL logic designs for multi-million gate high speed processors/ASICs. Knowledge of high speed compute (e.g. floating point vector processing units (VPU), GPU shader ...
Mixed Signal Verification Engineer
Posted 19 Sep 2024Job Description Role: Mixed Signal Verification Engineer Location: Sunnyvale, California Interview: Phone/Skype Emp Type: Contract JOB DESCRIPTION: Mixed signal Design Verification requirements: Fluent in system verilog real number modeling Familiarity with writing regression tests for analog behavioral model verification Familiarity with gener...
8+years of hands-on Verilog programming experience for ASIC, with proficiency in front-end Cadence tools and methodologies, along with a demonstrable track record of delivering complex RTL logic designs for multi-million gate high speed processors/ASICs. Knowledge of high speed compute (e.g. floating point vector processing units (VPU), GPU shader ...
8+years of hands-on Verilog programming experience for ASIC, with proficiency in front-end Cadence tools and methodologies, along with a demonstrable track record of delivering complex RTL logic designs for multi-million gate high speed processors/ASICs. Knowledge of high speed compute (e.g. floating point vector processing units (VPU), GPU shader ...